October 2026 Applications are open for the October 2026 VLSI design cohort Apply Now

Custom Layout with Virtuoso Layout Suite XL

You’ll be able to: Explain the semiconductor industry and the full ASIC & custom-IC flow; tell digital and analog design paths apart; read a chip spec.

Eligibility

Who Can Apply?

Final-year undergraduates
Graduates and layout engineers
Degree in, or current enrolment in:
Electrical & Electronic (EEE)
Electronics & Communication (ECE)
Electronics & Telecommunication (ETE)
Applied Physics / Electronics
Other related disciplines
Assumed knowledge:
Navigating Virtuoso and reading a schematic
At least one simple cell layout you have drawn yourself

Eligibility is advisory, not a gate. Enrolment is open — if you meet the knowledge bar for a course, you are welcome in it whatever year you are in.

Screening Process

Step 1: Mini-Exam
Step 2: Online Interview

Program Curriculum

Download brochure

Work in the connectivity-driven layout flow.

Generate layout from schematic connectivity.

Place devices with matching and guard rings.

Route custom analog interconnect.

Apply matching techniques for analog.

Use and configure PCells.

Drive layout with electrical constraints.

Iterate to a DRC-clean layout.

Finish layout for manufacturability.