A career pipeline built for impact

Semiconductor & VLSI Fundamentals

New entrants - 2nd/3rd-year EEE/CSE students and career-changers

Digital Design & Verilog Essentials

Aspiring RTL / digital-design engineers

Analog & Custom-IC Basics (Hands-On Virtuoso)

Aspiring analog / layout engineers

Functional Verification - SystemVerilog & SVA

Aspiring functional-verification engineers

RTL Simulation & Logic Synthesis

RTL designers moving toward implementation

Analog IC Design & Schematic Entry

Analog design engineers

Circuit Simulation with Spectre & ADE

Analog / mixed-signal engineers

Physical Implementation with Innovus

Aspiring physical-design / back-end engineers

UVM Verification Methodology

Verification engineers building reusable environments

Static Timing & DFT Signoff

Implementation / signoff engineers

Custom Layout with Virtuoso Layout Suite XL

Custom-layout engineers

Physical Verification & Extraction (Assura)

Layout / signoff engineers preparing for tapeout

Physical Verification & Tapeout Signoff

Back-end engineers taking a digital block to tapeout

1-Week Digital Design

Fresh university students (1st-3rd year) with no prior VLSI experience

A working 4-bit ALU - Verilog source, waveforms, write-up

1-Week Analog & Layout

Fresh university students (1st-3rd year) with no prior VLSI experience

A DRC-clean laid-out cell + schematic & sim results

2-Week VLSI Explorer

Fresh university students wanting a taste of both digital and analog

A portfolio piece: an RTL block + a laid-out cell