You’ll be able to: Explain the semiconductor industry and the full ASIC & custom-IC flow; tell digital and analog design paths apart; read a chip spec.
Who Can Apply?
Load a netlist, libraries and constraints into Innovus.
Define die/core area and place macros sensibly.
Build a robust power distribution network.
Place pins and I/O for clean connectivity.
Place standard cells and optimise for timing.
Read congestion maps and fix hotspots.
Understand what a good clock tree looks like.
Run CTS and post-CTS optimisation.
Route the design and resolve DRC/DRV issues.
Close setup/hold and hand off a routed design.
